ADC 学习笔记2
ADC sample Conversion Operation Modes
a cyclic,algorithmic architecture using two recursive sub-ranging sections
(RSD1,RSD2) .
http://img460.imageshack.us/img460/6007/figure259cr.jpg
each RSD resolves a single bit in each conversion clock
-> an overall conversion rate of two bits per clock cycle.
each RSD can run at a maximum clock speed of 5MHz,
-> a complete 12-bit can be accommodate in 1.2us,not including sample or post pocessing time.
Normal Operating Mode
two modes of mormal operation:
1.Single Ended Mode (CHNCFG bit=0) : Input MUX selects one of the eight analog inputs
directs it to the plus teminal of ADC core
minus terminal is connected to the VREFLO reference
ADC measures the voltage of the selected analog input
compares it against the (VREFH-VREFLO) reference voltage range.
2.Differential Mode(CHNCFG bit =1) :
ADC measures the voltage difference between two analog inputs
compares it against the (VREFH-VREFLO) reference voltage range.
The input is selected as an input pair: AN0/1,AN2/3,AN4/5 or AN6/7.
In this mode, plus terminal -> even analog input
minus termianl -> odd analog input
当然，这两种方式可以混和使用：
AN0/1 differential, AN2/3 single ended
AN4/5 dirrerential, AN6/7 single ended
Single Ended Samples
a ratio conversion.
digital result is proportional to the ratio of the analog input to
the reference voltage in the following diagram.
http://img460.imageshack.us/img460/9528/diagram19sy.jpg
Differential Samples
the digital result is proportional to the ratio of the difference in the
inputs to the difference in the reference voltages (VREFH and REFLO).
http://img460.imageshack.us/img460/9499/diagram28hu.jpg
Popularity: 16% [?]
Tags: BLDCRelated posts
