ADC Data Processing

ADC Data Processing

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ADC conversion result ->sent to an adder for offset correction.

adder substracts the ADC Offset(ADOFS0-7) register value from each sample
then the resultant value is stored in an ADC Result(ADRSLT0-7) register.

at the same time, raw ADC value and the ADRSLT values are checked
    for limit violations and zero-crossing.  appropriate interrupts are asserted..

The result value sign :
          ADC unsinged result minus the respective offset  register value (ADOFS0-7).
If the offset register is programmed to zero,
          the result register value is unsigned and equals  the cyclic converter unsigned result.
The  range of the ADRSLT is $0000-$7FF8(assuming the ADOFSn is set to all zeros).
This is = raw value of the ADC core.

          When the ADC is in Stop or Power-Down mode, each result register can only
be modified by the processor.
    that is : STOP bit = 1 in ADCR1
                  both PD0 and PD1 = 1 in ADC power register(ADCPOWER)

This write operation is treated as if it came from the ADC anlog core;
the limit checking,zero crossing ,offset registers function identically as when in normal operation.
       For example , if STOP bit = 1 and the processor writes ADRSLT5.
                               the data written to the ADRSLT5 is muxed to the ADC digitial logic inputs,
                                                    processed an stored into ADRSLT5
                                                                            as if the anlog core had provided the data.

Sequential Vs. Simultaneous Sampling
          
When  ADC is configured for sequential conversion, only one of the two ADCs operates
at any time. We can specify a scan sequence of up to eight conversions. Each of the conversions can select any of the eight input channels for conversion, with the result stored in the consecutive
result registers. can be either single ended or differential.

simultaneous conversion : both of the ADCs operate in parallel.
up to four conversion in a scan.  Each conversion can select any of the 8 inputs as long as both
ADCs are not sampling the same channel. The results are stored , two at a time ,in consecutive result register pairs.  
The first conversion is stored in ADRSLT0 and ADRSLT4. 
The next is ADRSLT1 and  ADRSLT5, and so on.
Each can be either single ended or differential ,in any combiantiom.

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