Scan Sequencing&Power-down mode
Initate: a SYNC signal from one of the on-chip timer channels
a write to the ADCR1 START bit.
Once initated, a sequence of up to 8 analog to digital conversions is begun.
If the scan parameter indicates more than one conversion,
a second conversion is immediately initiated following the completion of the first conversion.
The num of conversions in each scan is controlled via the Disable Sample(DS) field of ADSDIS
The sequence of channels to convert is controlled by the SAMPLEn fields of ADLST1&ADLST2.
If a scan is initiate while another scan is in process, the start signal is ignored
until the active conversion scan is complete, i.e.
until the Conversion In Process (CIP) bit in ADC Status register(ADSTAT) has changed 1 to 0
Low Power Operating Mode
Power-down mode is manually controlled via PD[2:0] and PUDELAY
Power Savings mode provides an automated way for the chip to dynamically
control ADC power-up/down status.
Only one of Power-down or Power Savings modes can be active at a given time.
Power-Down
The analog core of the ADC can be shut down for reduced power consumption
when the ADC module is not being used.
In Low Power mode current of the ADC is < 1uA.
Power down by setting the PD0,PD1,PD2 bits of the ADPOWER register to one.
Any conversions in progress by the affected ADC converter will be aborted
when PD0/PD1/PD2 are asserted.
Affected result registers may be corrupted if the power-down operation occurs late in
the conversion sequence, when those registers are normally updated.
Otherwise they will retain their previous value.
In a dual ADC configuration, if all PD0,PD1,PD2 are set, the voltage reference is powered down.
Note:
A wait of at least 25msec is required after powering up a voltage reference prior to
initiating a data conversion.
Failrue to do so will result in incorrect conversion results.
A delay of PUDELAY ADC clocks is required after powering up an ADC converter prior to
initiating a data conversion.
The PUDELAY is built into the ADC state machine,providing freedom from concern other
than being aware of the timing.
When the ADC reference is powered down, the output reference voltages are set to Low(VSSA)
and the ADC data output is driven low. The ADC analog core is powered up(PDn=0)on reset.
Any attempt to perform conversions while a converter is powerd down will result in undefined behavior.
Power-Down modes are cleared by resetting PD0,PD1,PD2 to zero.
Allow an amount of time equivalent to 13 ADC clocks or greater(specified in the PUDELAY field )
after clearing PD0 and/or PD1 before beginning conversions again.
assuming the voltage reference was not powered down.
Coming out of Low Power mode, the ADC does not retain any history of the last conversion completed before power-down.
A new scan sequence must be started with a SYNC pulse or a write to the START bit .
Note:
Powering up the ADC voltage references usually takes much longer than powering up the ADC. Additional delay must be provided, allowing VREFP,VREFMID,VREFN to stabilize.
If the bypass capacitors on these pins are not fully charged,ADC accuracy is adversely
affected.
This delay is usually longer than the number of ADC_CLK cycles specified by PUDELAY
for ADC power-up.
Asserting any of PD0, PD1 or PD2 will clear Power Saving Modes (PSM).
If PSM was at a logic 1 and only one of PD0 or PD1 are asserted,
then the other converter will power-up after a delay specified by PUDELAY.
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