Power Savings Mode

Power Savings Mode(PSM)

allows for automatic power-down/up of the ADC core,

The PSM feature can yield significant power savings when used correctly.

When an ADC conversion scan is completed the ADC core is automatically powered down.

When the next SYNC pulse (or write of 1 to the START bit of the ADCR1) occurs, the ADC core

is automatically powered up. ADC clock cycles are counted to provide for this power-up delay

and then another ADC scan sequence is started. SYNC pulses and writes to Start during a

conversion sequence are ignored.

ADCs are powered up in this mode only if needed for the programmed conversion. If only one

ADC converter is required, then only that ADC converter is powered up.

The voltage reference circuit remains powered up in this mode.

This is because it normally requires 25msec for the reference voltages to stabilize after power-up.

If PSM is asserted while a conversion is in progress,that conversion is unaffected and the ADC

will wait to enter PSM until the conversion is complete.

Contrast this to Power-Down mode, where conversions in progress on the affected converters are

aborted when PD0/1 are asserted.

PSM does not apply to Loop modes.Because the ADC does not stop once Loop mode is started,
PSM is useful only in Once/Trigger mode.

ADC STOP Operating Mode
Any conversion sequence in progress can be stopped by setting the ADC STOP bit int the ADCR1.
Any further AYNC pulses or writes to the START bit are ignored until the ADC STOP bit is cleared.

After the ADC is in ADC STOP mode, the results registers can be modified by writes from the processor.
These write to the result register in the ADC STOP mode is treated as if the analog core supplied the data.Therefore ,limit checking ,zero crossing ,and associated interrupts can occur if enabled.

Technorati Tags: BLDC, topkong

Popularity: 15% [?]